1. Field of the Invention
The present invention relates to reliability and packaging of electronic devices, particularly integrated circuit devices. More particularly, the present invention relates to a methodology for verifying the reliability of the interface between bond pads and other structures in integrated circuits. The present invention further resolves potential mismatches which can occur between revisions of masks used to form an electronic device and corresponding revisions of the test program used for evaluating the device.
2. Discussion of the Related Art
Integrated circuit devices manufactured on silicon wafers are typically separated into individual IC chips and assembled into packages. One of the principal functions of the package is to allow connection of the chip to a circuit board or other electronic product. Such connection can generally not be made directly from the chip to the target product due to the thin, fragile microscopic metal structure used to interconnect the several components on the chip surface. Many metal leads on the IC are typically about 0.6 xcexcm thick and less than 1.0 xcexcm wide. Indeed, many of the surface features of current production integrated circuits are xe2x80x9csub-micronxe2x80x9d or less than 1.0 xcexcm in width. Therefore, xe2x80x9cbond padsxe2x80x9d approximately 100 uM square are typically placed around the periphery of the IC chip. xe2x80x9cBond wiresxe2x80x9d are then used to connect the IC chip to the packaging frame. This frame is then usually xe2x80x9cencapsulatedxe2x80x9d with either plastic or ceramic materials to complete the packaging process.
A common IC lead and bond pad material is aluminum that is deposited and patterned during chip fabrication. The gold or aluminum bond wire used to connect the bond pad to the package frame is currently available is typically in the range of 17 to 30 xcexcm in diameter, many times larger than the integrated circuit""s surface wiring. Bond wires are typically connected to the bond pads by means of metal balls (gold) or wedge bonds (aluminum) formed at the end of the bond wires and applied to the bond pad. Bond wires may be attached by thermosonic bonding, or other wire attachment methodology well known to those of ordinary skill in the art.
The first problem which occurs in some integrated circuit devices is xe2x80x9ccrateringxe2x80x9d in the layers under the bond pads. Cratering is generally a fracture of the silicon and dielectric oxide layers under the bond pad. This phenomenon is sometimes referred to as xe2x80x9cbond pad crateringxe2x80x9d. While studies to determine exact mechanisms for crater initiation and propagation are still underway, an overview of some of the known mechanics of crater formation is discussed as follows.
One process which has been shown to be contributory to crater initiation is the use of thermosonic attachment methodology for attaching bond wires to bond pads. Thermosonic bonding employs ultrasonic vibration, typically about 60-120 kHz, to form the bond This dynamic is shown in FIG. 1. It illustrates a cross-section through an integrated circuitxe2x80x94IC (1). The device is formed of a plurality of layers and includes one or more bond pads (2). In this example the layers of the IC (1) include silicon substrate (4), field oxide layer (6), BPSG layer (8), passivation layer (9) and plastic encapsulant (10). A wire bond (12) is shown including bonding ball (14). The center of the die is located toward the direction labeled xe2x80x9cZxe2x80x9d. This listing of layers in the device is not meant to be exhaustive but is illustrative of some of the several layers of a micro-electronic device known in the art.
During the wire bonding process wire bond ball (14) is attached to bond pad (2) utilizing, for example, thermosonic bonding. The bonding process can induce microcracks (20). With repeated thermal cycling these microcracks can propagate (24) in the layers beneath the bond pad causing chip failure. Some of these mechanisms are described below.
FIGS. 2A, 2B, and 2C are plan views of a section of a packaged IC directly beneath a bond pad after the chemical removal of the bond wire ball which illustrates microcrack initiation and propagation. FIGS. 2Axe2x80x2, 2Bxe2x80x2, and 2Cxe2x80x2 are cross-sections through the same section with the bond pads and bond wires intact.
The physical propagation of a microcrack into a full-blown pad crater is shown in FIG. 2. FIGS. 2A and 2Axe2x80x2 show a microcrack (20) that has been formed in a layer immediately beneath bond pad (2). With repeated thermal cycling this microcrack propagates in the direction shown (26) in FIGS. 2B and 2Bxe2x80x2. With continued thermal cycling, crack propagation moves in a generally elliptical manner (FIG. 2B) and downward (FIG. 2Bxe2x80x2). It should be noted that this elliptical crater (FIG. 2xe2x80x2) is formed with its short axis aligned along a line originating substantially near the chip center.
FIG. 3 shows a scanning electron microscope (SEM) image of two areas underlying bond pads of an IC (1) which failed due to bond pad cratering. This generally elliptical crater formation, and its alignment with the center of the device is clearly shown in these photomicrographs. Cratering often results in intermittent contact between the internal IC wiring and the bond pad thus inducing a subtle and insidious reliability problem by precluding reliable electrical contact between the chip""s surface wiring and the bond pads which in turn precludes a reliable contact with the bond wires and the package.
Finally, the formation of craters is a progressive process. This means that while a predisposition for crater formation in the form of microcracks may be present when the chip is going through the chip test procedures during manufacturing, a crater resulting in electrical failure may not have yet formed. This predisposition is referred to herein as xe2x80x9ccrater jeopardyxe2x80x9d. It is only after a substantial number of thermal cycles that the crater actually forms and attendant chip failure occurs.
It will be understood by those having skill in the art that the bond pad cratering phenomena previously discussed are still under investigation. While it is generally believed that microcracks are initiated by stresses induced by the dynamic force of the gold ball or aluminum wedge bond at touch-down impact, the static force applied after touch-down, the level of ultrasonic energy, mechanical vibrations before or after bonding, and/or the hardness of the gold ball in relation to the pad, the role which each of these mechanisms plays in crack/crater formation is still under investigation. Moreover, while the formation of cracks is believed to be dependent on the bonding mechanism, bond parameters, the thickness of the wire bond pad and characteristics of the wire bond material being bonded, the roles of each of these mechanisms is also under investigation. Furthermore, continued research has shown that thermal cycling and shock during the plastic encapsulation process may play a role in propagating bond pad crater formation.
While a number of mechanisms and procedures are currently being investigated to prevent bond pad crater formation and attendant chip failure, given the insidious nature of the onset of crater formation what is especially important is a practical methodology to detect microcracks under the bond pads during the manufacturing process. The methodologies previously utilized to detect bond pad crack/crater formation are insufficient, laborious and destructive as will now be described.
A first prior art methodology for monitoring crater jeopardy is by destructive decapsulation and deprocessing including the chemical removal of the ball bonds followed by visual inspection and high magnification. The results of one such SEM examination of the area under two bond pads suffering from bond pad crater formation is shown in FIG. 3. While this monitoring for crater jeopardy is particularly effective, it is the both laborious and destructive, and renders the device inoperative and unfit for further service. Clearly, this destructive and labor-intensive process cannot be effective for shippable products.
The second prior art methodology has been to undertake one or more functional tests of the chip subsequent to encapsulation. As previously discussed, one of the factors known to be important in bond pad crater formation is thermal cycling. Accordingly, it may require hundreds or even thousands of device heat/cool cycles before microcracks develop into full-blown bond pad craters with an attendant bond pad failure sufficient to trigger a functional test. Moreover, utilization of this test methodology has been shown to reduce the life expectancy of the device.
Finally, there exist special test structures for electrical detection of the problem. These usually include continuity tests or tests for electrical leakage by structures under the pad. While these tests structures have in some cases been shown to be effective for the detection of larger cracks and bond pad craters, they are not the optimal solution to the problem. In the first place, the use of these tests structures introduces one or more additional processes during manufacturing. Secondly, the accuracy and reliability of these test structures for detecting the microcracks shortly after their inception has not been proven.
A second problem not fully solved in the prior art comes about when a product is changed due to mask revisions which often results in a corresponding revision of the test program of the product. The importance of using the correct test program on the revised product will readily be understood, i.e., mismatches between the two are to be avoided.
Therefore, what is needed is a method to detect the formation of microcracks in the substrate immediately below the bond pad or bond pads of an IC. The methodology should enable the testing of each device during the manufacturing process without resorting to destructive test techniques. Moreover, the methodology should be capable of being implemented without unduly complicating or lengthening the normal manufacturing process for such devices. The methodology should not require additional bond pads or leads for the associated package.
What is further needed is a methodology to prevent the potential mismatch between actual mask revisions and the corresponding revision of the test program.
An especially elegant solution to these problems would be a single solution capable of simultaneously addressing and solving these two disparate issues.
The present invention teaches a methodology whereby 100 percent of the pads on chips undergoing manufacture can be effectively tested for the formation of cracks, most importantly small cracks, beneath the wire bond pad. The methodology is non-destructive in nature and does not overly complicate the manufacturing process. An additional benefit to the methodology is the capability to resolve differences between an actual mask revision and the corresponding revision of a test program.
The invention includes a polysilicon meander with a xe2x80x9cdown and backxe2x80x9d pattern or a radial in/out pattern is formed beneath each bond pad. The meander pattern covers all the area beneath each bond bad and is connected on one end to the bond pad itself. The other end is connected to the source and one input terminal of a two-input NAND gate. The pad is driven high during testing, and a continuous meander causes one of the input terminals of the NAND gate to go high. If the other input terminal of the NAND gate is also driven high, there is then a low resistance between the source of the NAND gate which is connected back to the pad through the meander and the drain of the NAND gate which is connected to ground. Thus, a current would flow from the pad to the ground through the meander. Clearly, a fractured meander will not permit current to flow and a break would be detected provided the length of the fracture is greater than the pitch of the meander.
Connected to the other input terminal of the two-input NAND gate is the output terminal of an OR gate with two plural-input AND gates. The second input terminal of the NAND gate will go high if all of the input signals (xe2x80x9cmaster keysxe2x80x9d, i.e., hard wired patterns) to either AND gate are driven high. Accordingly, a first master key pattern applied to the pads connected to a six input terminal AND gate, for example, would cause the output signal of that AND gate to go high and trip the OR gate and two-input NAND gate. The test sequence then individually tests each pad for craters except those pads to which the first master key is applied. When the test sequence is finished on all pads except the master key pads, a second master key is provided to the six input terminals of the other AND gate so that the six pads connected to the first AND gate can be checked.
The previously discussed test sequences not only disclose crater jeopardy beneath the bond pad, but also reveals a potential mismatch between actual mask revision and the corresponding revision of the test program.
Of particular note is the fact that the implementation of the present invention does not require significant additional space on the chip, nor extra bond pads or package leads thereby precluding any loss of feature density on the chip itself and packaging costs. Moreover, the testing step used to implement the methodology is not particularly time-consuming, thereby aiding in economy of manufacture.
It should be noted that the two input NAND gate, two input OR gate, and six input AND gates described above that are required to implement at least one aspect of the present invention are very small features compared to bond pads even when the attendant wiring is added.
The present invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art, there is shown and described embodiments of this invention by way of the illustration of the best mode to carry out the invention. The invention is capable of other embodiments and its several details are capable of modifications without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.